1. Technical Field
The disclosed embodiments relate to ESD protection circuits.
2. Background Information
An electrostatic discharge (ESD) protection circuit commonly referred to as an active RC triggered clamp can be used to protect functional circuitry from damaging high voltages caused by electrostatic discharge events. If a voltage between two terminals of an integrated circuit increases at an adequate rate due to an ESD event, then an RC circuit triggers and turns on a large N-channel field effect transistor (sometimes referred to as a “bigFET”). The bigFET shunts an ESD current between the two terminals and clamps the voltage across the terminals to a voltage that is safe for the functional circuitry. Although multiple such active RC triggered clamp circuits can be stacked, such active RC triggered clamps are generally used in applications where the supply voltage is relatively low (for example, three volts). If such stacked active RC triggered clamps were to be used in an application having a higher supply voltage of twenty volts for example, then the bigFETs would likely have to be made to be undesirably large because bigFETs in active RC triggered clamps operate in the normal conductive mode.
If an active circuit that operates from a relatively high operating supply voltage is to be protected from ESD events, then a silicon controlled rectifier (SCR) circuit could be used as is known in the art. Unfortunately, SCR ESD protection circuits when activated have holding voltages that can be lower than the relatively high operating supply voltage. This is undesirable. If during normal circuit operation a large voltage transient (that is not due to an ESD event) were to appear across the supply voltage terminals of a circuit protected by an SCR ESD protection circuit, then the SCR ESD protection circuit might engage and pull the supply voltage below the operating voltage of the active circuit. Some means must therefore generally be provided to prevent such large voltage transients from being imposed across the supply voltage terminals. Having to provide this extra circuitry is undesirable.
FIG. 1 (Prior Art) is a circuit diagram of a conventional ESD protection circuit 1 used to protect functional circuitry that operates from the relatively large operating supply voltages described above. ESD clamp circuit 1 is sometimes referred to as a “gate grounded NMOS” (GGMOS or GGNMOS) protection circuit because the gate of each of the N-channel field effect transistors 2-4 is coupled to the source of the transistor. FIG. 2 is a simplified cross-sectional diagram of the circuit of FIG. 1. Under an ESD event, the three transistors 2-4 conduct in the snap-back or parasitic bipolar mode such that an ESD current is conducted from the VCC supply voltage terminal 5, through transistor 2, through transistor 3, though transistor 4, and to ground terminal 6.
FIG. 3 (Prior Art) is a cross-sectional diagram of one of the stages of the GGMOS protection circuit of FIG. 3. Under a high voltage condition, the electric field across the reverse-biased drain 7 to body 8 depletion region increases to the point that an avalanche breakdown mechanism generates change charge carriers. These carriers result in a current flow that flows into the base of a parasitic bipolar NPN transistor 9. The N-type collector of parasitic transistor 9 is the N+ type drain 7. The N-type emitter of parasitic transistor 9 is the N+ type source 10. The P-type base is the P-type material of the body 8 of the N-channel field effect transistor. Parasitic transistor 9 is depicted with the bipolar transistor symbol in FIG. 3. The base current turns on the bipolar transistor, which in turn causes a large collector current to flow across the drain-to-body junction. This current serves to contribute to the necessary base current to sustain forward biasing of the base-to-emitter junction of the parasitic transistor. Accordingly, whereas a higher drain-to-source voltage (called the trigger voltage) is required to initiate bipolar transistor conduction, once initiated the bipolar transistor conduction is sustained unless the drain-to-source voltage drops below a lower voltage (called the holding voltage). This characteristic of transistor turn on and conduction is commonly referred to as “snap-back”.
Stacking three such GGMOS circuits such as in the circuit of FIG. 1 multiplies each of trigger voltage and the holding voltage by the number of circuits stacked. The circuit of FIG. 1 therefore has a trigger voltage that is three times the trigger voltage of the single stage circuit of FIG. 3. The circuit of FIG. 1 therefore has a holding voltage that is three times the holding voltage of the single stage circuit of FIG. 3. Unfortunately, the multiplied trigger voltage of the stacked circuit of FIG. 1 may be so high that damage may occur to the functional circuitry to be protected before the ESD protection circuit of FIG. 1 triggers and performs its current shunting function.
FIG. 4 (Prior Art) is a diagram of an ESD protection circuit that has a lower trigger voltage. The ESD protection circuit is sometimes referred to as a gate-driven NMOS (GDNMOS) circuit or a gate-coupled NMOS (GCNMOS) circuit. A resistor 11 is disposed between the gate 12 and the source 13 as illustrated in FIG. 4. The structure has a capacitance 14, such as the inherent drain-to-gate overlap capacitance of the transistor. During an ESD event, a rapid rise in the voltage on drain 24 is coupled to gate 12 by the capacitance 14, and current flow across resistor 11 causes a gate-to-source voltage. This gate-to-source voltage induces a channel to form under the gate 12 and allows an amount of surface current 15 to flow from drain 24. Current 15 serves to reduce the trigger voltage of the circuit. For additional information on this effect, see: 1) “Design Methodology and Optimization of Gate-Driven NMOS ESD Protection Circuits In Submicron CMOS Processes”, IEEE Transactions on Electron Devices, vol. 45, no. 12, pages 2448-2456 (December 1998) by Julian Zhiliang Chen et al.; and 2) U.S. Pat. No. 5,982,217; 3) U.S. Pat. No. 5,838,146; and 4) U.S. Pat. No. 5,631,793. Where larger holding and trigger voltages are required than are provided by a single stage, the circuit of FIG. 4 can be stacked. FIG. 5 (Prior Art) illustrates a conventional stacked GCMOS ESD protection circuit having three stages 16-18.